This application is related to application Ser. No. 08/509,586 entitled "A Method of Estimating signal Quality for a Direct Sequence Spread Spectrum Receiver;" application Ser. No. 08/509,587 entitled "Short Burst Acquisition Circuit for Direct Sequence Spread Spectrum Links;" application Ser. No. 08/509,590 entitled "Short Burst Direct Acquisition Direct Sequence Spread Spectrum Receiver;" and application Ser. No. 08/509,589 entitled "A/D Reference Level Adjustment Circuit to Maintain an Optimum Dynamic Range at the A/D," all of which are incorporated by reference and are filed concurrently herewith and assigned to the assignee hereof.
This application is related generally to systems and methods for receiving signals having data coded therein, and in particular to systems and methods for determining and/or adjusting a clock used to extract the data from a received signal.
It is well known for signals to be transmitted in which data to be transmitted is used to modify a carrier signal. For example, digital data may be used to key a phase shift keyed modulator of a carrier frequency. Decoding of such modulated signals generally requires acquisition and tracking of the carrier frequency and demodulating of the carrier signal to return the original data signal. As is well known, the demodulating may take more than one step as the received signal may first be down converted to an intermediate frequency and subsequently demodulated to baseband. This baseband signal may then be processed in a correlator to remove an overlying spectrum spreading pseudo noise sequence. Such sequences are well known in the art and are referred to as spread spectrum. They are often applied as phase shift keyed ("PSK") modulation over the data modulation. The spreading sequence usually has a higher rate than the data modulation, often much higher. As is well known in the art, the data signal may be a series of transitions in phase or amplitude or frequency, each transition signifying the transmission of one or more portions of the data signal. For example, in a Binary Phase Shift Keyed system, the carrier signal is phase shift keyed to represent the data. In such a system sending digital data, the modulating signal causes the phase of the carrier signal to be advanced (or retarded) a predetermined number of degrees of phase to represent either a 0 or 1 binary number. In Quartary Phase Shift Keyed systems, one of four phase transitions are possible during each modulating cycle, each transition representing two bits of digital data. During each transition, or modulating signal cycle, the carrier signal contains one "symbol" which may represent one or more bits of data.
Often the modulating signal is applied to the carrier signal without regard to the phase relationship between the two signals. Thus, even when the receiver acquires the carrier signal, the receiver may not necessarily know therefrom the beginning of each symbol within the data signal. In noisy communications environments, the presence of noise on the received signal may make it difficult to determine from examining any particular symbol where the symbol begins. In prior art systems, it is known to examine plural symbols within a received signal to attempt to average the effect of noise and to thereafter remove the noise from the data signal within the noisy environment.
In order to demodulate a received signal in straightforward fashion, the receiver should know the modulation rate, i.e., how often to expect to receive a new symbol. Accordingly, the receiver may be set to generate a clock pulse the frequency of which coincides with the frequency of the modulation (or the symbol rate). This clock may be called a bit clock because it has a frequency which should match the frequency at which new symbols are received. Oftentimes, the receiver may also generate other clocks as needed from the bit clock. Merely having a bit clock, however, is generally insufficient because the bit clock must usually be synchronized with the incoming symbols. Unless the bit clock is properly synchronized, the signal may suffer relatively large losses. In the case of spread spectrum, demodulating the signal is generally possible only if the bit clock is aligned such that the signal samples being used fall somewhere on the correlation peak. Once bit synchronization can be obtained, however, the various receiver elements can be set to align the decoding circuits so that decoding and similar evaluations of the received symbols may be accomplished at the most useful time within the symbol period. (For example, the bit synchronization may be critical in determining when to use an analog-to-digital circuit to sample the magnitude of the input signal.)
In digital systems, a received signal may be sampled at a frequency greater than the Nyquist frequency and the digital samples represent the received signal. In such systems, a sequence of symbols may be represented by a sequence of samples. The sequence of digital samples may be evaluated to locate which set of the samples best coincides with an event expected within each symbol (start, end, transition, etc.). For example, and with reference to FIG. 1, a received signal 10, after correlation processing, may have the shape shown. Samples 12 of the signal are taken at a periodic rate and digitally stored and processed. For the signal of FIG. 1, peaks 14 in the signal represent the points of maximum correlation between the PN reference and the signal spreading sequence for each symbol. By examining the sample data in one or more symbols, a receiver can determine where the peaks 14 occur and adjust its decoding circuits to center the peaks within the symbol period. For the signal of FIG. 1, the peaks occur near the eighth sample, and accordingly, the eighth sample will have the maximum value. The decode circuitry can then be reset to center the symbol period appropriately.
Note that in the sampling system of FIG. 1, no sample occurred exactly at the peak. Generally speaking, it is desirable to adjust the decoding circuits so that they are decoding the signal as closely to the peak as possible. Accordingly, the prior art has developed many different methods for centering the peaks. In one prior art scheme, a voltage controlled oscillator is used to adjust the phase of the A-to-D sampling to match the detected peaks. Such a scheme has achieved some success in obtaining fine resolution of the phase but generally requires costly analog components. Another prior art scheme oversampled the A-to-D input and used the closest of these oversamples. Such a scheme generally requires very fast, relatively expensive and high power consumption A-to-D devices. Still another prior art scheme uses digitally programmable delay lines to time shift the sampling clock or input signal. Such a scheme generally required relatively expensive and large components to implement.
Accordingly, it is an object of the present invention to provide a novel method and apparatus of acquiring bit synchronization while minimizing additional circuitry and power consumption.
It is another object of the present invention to provide a novel method and apparatus to acquire bit synchronization with a reduced number of circuit components and complexity when compared to some prior art bit synchronization schemes.
It is still another object of the present invention to provide a novel method and apparatus for demodulating and decoding phase shift keyed signals without a relatively high speed A-to-D device to adjust bit synchronization.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.